Efficient (Masked) Hardware Implementation of Grain-128AEADv2

Table 1

Clock periods (ns) and critical paths (CP.) of the straightforward version of Grain-128AEAD and Grain-128AEADv2.

Cipher		x1	x2	x4	x8	x16	x32	Plat.
Grain-128AEAD [8]	Period	0.49	0.61	0.64	0.69	0.77	0.84	ASIC
	CP.
Grain-128AEADv2	Period	0.478	0.480	0.492	0.520	0.591	0.597	ASIC
		2.76	2.81	2.85	2.90	3.08	4.04	FPGA
	CP.