Efficient (Masked) Hardware Implementation of Grain-128AEADv2

Table 2

Evaluation results on ASIC.

	Period	Area	Throughput	Efficiency	Technique
x1	0.44	5975	1.14	0.19	Straightforward
x2	0.46	5705	2.17	0.38
x4	0.46	6678	4.35	0.65
x8	0.48	7676	8.33	1.09
x16	0.57	8692	14.55	1.61
x32	0.60	13381	26.67	1.99
x1	0.41	6028	1.22	0.20	Galois transformation
x2	0.41	6399	2.44	0.38
x4	0.44	6742	4.55	0.66
x8	0.45	7744	8.89	1.15
x16	0.47	10194	17.39	1.67
x1	0.42	6192	1.19	0.19	Pipeline-like pre-computation
x2	0.41	6419	2.44	0.38
x4	0.42	6877	4.76	0.69
x8	0.43	8116	9.30	1.15
x16	0.44	10559	18.18	1.72
x32	0.49	15249	32.65	2.14
x1	0.47	10415	1.06	0.10	Masking straightforward
x2	0.48	11192	0.69	0.06
x4	0.49	13701	1.36	0.10
x8	0.57	17471	2.34	0.13
x16	0.61	25788	4.37	0.17
x32	0.67	44246	7.96	0.18
x1	0.43	11615	1.16	0.10	Masking pipeline-like pre-computation
x2	0.44	13305	2.27	0.17
x4	0.45	16866	4.44	0.26
x8	0.48	22722	8.33	0.37