Efficient (Masked) Hardware Implementation of Grain-128AEADv2

Table 3

Evaluation results on FPGA.

	Period	Area			Throughput	Efficiency	Technique
		x1	2.76	158	403			629	0.18	1.15	Straightforward
x2	2.81	168	463	625	0.36	2.12
x4	2.85	191	547	623	0.70	3.67
x8	2.90	201	634	625	1.38	6.86
x16	3.08	355	1073	615	2.60	7.32
x32	4.04	502	1730	614	3.96	7.89
x1	2.68	185	611	632	0.19	1.01	Galois transformation
x2	2.72	214	669	627	0.37	1.72
x4	2.78	224	779	627	0.72	3.21
x8	2.80	274	853	632	1.43	5.21
x16	2.91	341	1148	703	2.75	8.06
x1	2.67	212	623	632	0.19	0.88	Pipeline-like pre-computation
x2	2.71	214	694	632	0.37	1.72
x4	2.76	236	794	635	0.72	3.07
x8	2.80	263	907	640	1.43	5.43
x16	2.89	371	1216	719	2.77	7.46
x32	3.19	537	1849	760	5.02	9.34
x1	2.81	210	683	1098	0.06	0.28	Masking straightforward
x2	2.90	350	1286	1177	0.11	0.33
x4	3.01	464	1565	1337	0.22	0.48
x8	3.22	593	1888	1648	0.41	0.70
x16	3.66	840	2681	2278	0.73	0.87
x32	4.71	1176	4139	3513	1.13	0.96
x1	2.93	226	774	1104	0.17	0.76	Masking pipeline-like pre-computation
x2	2.94	414	1428	1195	0.34	0.82
x4	3.01	506	1875	1370	0.66	1.31
x8	3.24	738	2643	1718	1.28	1.72