| while(mbno < total_mbs+n) |
| // where n = no. of pipeline stages - 1 |
| // DMA0 Stage |
| If(mbno < total_mbs) |
| Configure DAM0 ( ) // for current MB |
| If(mbno > 0) |
| Poll DMA0( ) // for previous MB |
| End If |
| exeute DMA0( ) // for current MB |
| If(last MB) |
| Poll DMA0( ) // for current MB |
| End If |
| End If |
| // MCE Stage |
| If(slice is P_TYPE) |
| mbno_mce = mbno-1; |
| If(mbno_mce >= 0 && mbno_mce < total_mbs) |
| If(mbno_mce > 0) |
| If(current MB is inter type) |
| Configure MCE( ) // for current MB |
| End If |
| If(prvious MB is inter type) |
| poll MCE( ) // for previous MB |
| End If |
| End If |
| If(current MB is inter type) |
| exeute MCE( ) // for current MB |
| If(last MB) |
| Poll MCE( ) // for current MB |
| End If |
| End If |
| End If |
| End If |
| // VMAU Stage |
| mbno_vmau = mbno-2; |
| If(mbno_vmau >= 0 && mbno_vmau < total_mbs) |
| Configur VMAU( ) // for current MB |
| If(mbno_vmau > 0) |
| poll VMAU( ) // for previous MB |
| End If |
| exeute VMAU( ) // for current MB |
| If(last MB) |
| poll VMAU( ) // for current MB |
| End If |
| End If |
| // DBLK Stage |
| mbno_dblk = mbno-3; |
| If(mbno_dblk >= 0 && mbno_dblk < total_mbs) |
| Configur DBLK( ) // for current MB |
| If(mbno_dblk > 0) |
| Poll DBLK( ) // for previous MB |
| End If |
| exeute DBLK( ) // for current MB |
| Entropy encoding( ) // for current MB |
| If(last MB) |
| poll DBLK( ) // for current MB |
| Endif |
| End If |
| // DMA12 Stage |
| mbno_dma12 = mbno-4; |
| If(mbno_dma12 >= 0 && mbno_dma12 < total_mbs) |
| Configur DMA12( ) // for current MB |
| If(mbno_dma12 > 0) |
| Poll DMA12( ) // for previous MB |
| End If |
| exeute DMA12( ) // for current MB |
| If(last MB) |
| poll DMA12( ) // for current MB |
| End If |
| End If |
| mbno++; |
| |
