The On-Chip D-LMS Filter Design Method of Wireless Sensor Node Based on FPGA

<div>Simulation validation diagram of filter orders. (a) Simulation signal diagram of 0 dB noise explosion seismic wavelet. (b) Simulation results of SNR after filtering with different orders. (c) Simulation result graph of a filter with an order <i>N</i> = 12.</div>

Shock and Vibration

fig6

Figure 6

Figure 6: The On-Chip D-LMS Filter Design Method of Wireless Sensor Node Based on FPGA 