Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation

Table 1

Charge consumption results for the standard (std.) and the BBM delay cells depicted in Figure 9 measured for one rising and one falling slope. The columns denoted by the percent sign represent the percentage of the standard delay cell’s consumption.

[ns]	std. [fAs]	PtNt [fAs]	[%]	PtNf [fAs]	[%]	PfNt [fAs]		PfNf [fAs]
	34^*	45^*	—	78^*	—	44^*	—	97^*	—
	26	30	115	87^*	—	30	115	62^*	—
	32	34	106	34	106	35	109	42	131
	39	38	97	35	90	39	100	38	97
	65	45	69	42	65	46	71	46	71
	77	58	75	49	64	58	75	55	71
	113	86	76	67	59	86	76	93	82
	153	118	77	89	58	118	77	130	85
	186	142	76	108	58	143	77	177	95

Delay target was not achieved.