Low Power Adder Based Auditory Filter Architecture

Table 3

Existing and proposed auditory filter architectures for cochlea processor.

Architecture using input pattern generator and regular full adder in summation block	Existing	Proposed	% gain
	DA based filter architecture using XOR gate [12]	DA based filter architecture using MUX
	and regular full adder architecture [17]	and reconfigured full adder architecture
Area (Sq. microns)	540.00	555.48	−2.86
Delay (ns)	7.96	7.74	2.76
Dp (uW)	28.18	28.32	−0.4
Lp (uW)	5.21	4.42	15.16
Tp (uW)	33.40	32.74	1.97

Note: design was mapped to TSMC 65 nm technology node.
Dp: dynamic power; Lp: leakage power; Tp: total power; ns: nanoseconds; uW: micro-Watt.