Empirical Mode Decomposition and Neural Networks on FPGA for Fault Diagnosis in Induction Motors

Table 4

Resource usage of the FPGA.

Resource utilization	EMD	ADALINE	FFNN	Total used	Available	Percentage
Programmable logic	3,731	3,198	1,582	8,511	29,504	28.85
LUTS	11,211	7,437	4,795	23,443	29,504	79.45
Multipliers	30	4	2	36	36	100
Clock cycles	984,564	84,340	237	Total	1,069,141