FPGA Implementation of UFMC Based Baseband Transmitter: Case Study for LTE 10MHz Channelization

Table 2

Post-place and route results.

System Component	Slice; Registers	Slice LUTS	DSP48 Blocks	BRAMs	Clock; Cycles/PRB	Frequency; (MHz)
Process 1	27	28	0	0	68	540
Process 2	33	233	4	3	336	440
Process 3	714	720	40	0	514	364
Processes 4 & 5	136	152	20	0	514	372
Total	910	1133	64	3	514 (with pipelined architecture)	364 MHz