Deep-Sea: A Reconfigurable Accelerator for Classic CNN

Table 4

Accelerator resource consumption statistics under 4-16 architecture.

Name	Slice LUTs	Slice registers	Slice	LUT logic	DRAM	BRAM	DSPs
CONV array	24391	43515	15032	20446	3945	0	540
AP array	27065	23280	9106	26495	570	0	80
PE	210	530	218	144	66	0	9
2D-PE	1693	3090	979	1415	278	0	36
TPOCM	1584	2208	1193	1584	0	128	0
Line	555	1573	467	555	0	4	0
TPOCM CTL	2262	2312	1332	1947	315	0	15
AP CTL	1993	242	909	1993	0	0	0
CONV array CTL	304	381	218	304	0	0	0
Global CTL	893	1060	376	893	0	8	0
MEM management	1221	1377	587	1214	7	8	0
Total	64391	81460	25105	59043	5357	155	673