Design and Implementation of Shared Memory for Turbo and LDPC Code Interleaver

<table class="table-group" id="tab2"><tr><td><table class="table"><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr><td class="align_left">Parameters</td><td class="align_center">Value</td></tr><tr><td class="align_left" colspan="2"><hr/></td></tr><tr><td class="align_left">Technology</td><td class="align_center">28 nm</td></tr><tr><td class="align_left">SRAM size</td><td class="align_center"><span style="width: 46.9156ptpx;"><svg height="15.0208pt" id="M26" style="vertical-align:-3.429399pt" version="1.1" viewbox="-0.0498162 -11.5914 46.9156 15.0208" width="46.9156pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M241 635C89 635 35 457 35 312C35 153 89 -12 240 -12C390 -12 443 166 443 312C443 466 390 635 241 635ZM238 602C329 602 354 454 354 312C354 172 330 22 240 22C152 22 124 173 124 313S148 602 238 602Z"></path></g><g transform="matrix(.013,0,0,-0.013,6.24,0)"><path d="M113 -12C146 -12 170 11 170 46C170 78 146 103 114 103S58 78 58 46C58 11 82 -12 113 -12Z"></path></g><g transform="matrix(.013,0,0,-0.013,9.204,0)"><path d="M384 0V27C293 34 287 42 287 114V635C232 613 172 594 109 583V559L157 557C201 555 205 550 205 499V114C205 42 199 34 109 27V0H384Z"></path></g><g transform="matrix(.013,0,0,-0.013,15.444,0)"><path d="M447 623H65C61 580 56 530 47 475H76C100 541 106 550 172 550H388C308 376 196 170 91 -1L98 -12L172 -2C268 204 360 408 455 611L447 623Z"></path></g><g transform="matrix(.013,0,0,-0.013,23.862,0)"><path d="M538 96L524 119C492 88 454 63 446 63C439 63 434 70 440 101C463 223 491 341 518 448H508L433 422L401 276C355 192 240 56 188 56C163 56 154 89 163 133C184 233 207 338 235 443L230 448L152 424L58 17C40 -60 23 -143 23 -185C23 -241 42 -261 63 -261C92 -261 117 -241 125 -227L124 -221C109 -209 89 -165 89 -103C89 -55 96 -13 105 26H107C121 -3 134 -12 151 -12C172 -12 194 -5 221 16C279 61 330 124 384 194H386C381 159 377 141 368 105C343 3 363 -12 383 -12C416 -12 486 35 538 96Z"></path></g><g transform="matrix(.013,0,0,-0.013,31.078,0)"><path d="M797 0V26C739 32 732 36 732 103V296C732 394 682 449 605 449C576 449 550 437 529 423C504 407 475 389 446 366C425 418 382 449 334 449C303 449 279 437 253 421C222 403 201 385 180 371V452C135 432 85 419 41 411V388C99 379 102 374 102 310V103C102 38 93 32 27 26V0H238V26C189 32 180 38 180 103V338C210 363 250 390 289 390C351 390 377 348 377 275V103C377 37 368 32 306 26V0H520V26C465 32 456 38 456 101V296C456 314 455 326 453 338C491 369 529 390 565 390C628 390 653 345 653 274V107C653 36 642 32 583 26V0H797Z"></path></g><g transform="matrix(.0091,0,0,-0.0091,41.765,-5.741)"><path d="M414 144C384 79 371 75 317 75H135L276 221C367 316 408 376 408 465C408 570 327 635 237 635C179 635 131 609 100 575L42 494L67 471C94 510 138 565 205 565C277 565 321 517 321 435C321 348 258 270 195 195C146 137 88 81 33 26V0H411C423 44 433 88 446 135L414 144Z"></path></g></svg></span></td></tr><tr><td class="align_left">Voltage</td><td class="align_center">0.9 V</td></tr><tr><td class="align_left">Frequency</td><td class="align_center">50 MHz</td></tr><tr><td class="align_left" rowspan="2">Throughput</td><td class="align_center">800 Mbps for turbo</td></tr><tr><td class="align_center">1600 Mbps for LDPC</td></tr><tr class="table-tr"><td colspan="2"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Wireless Communications and Mobile Computing

tab2

Table 2

Table 2: Design and Implementation of Shared Memory for Turbo and LDPC Code Interleaver 