Design and Implementation of Shared Memory for Turbo and LDPC Code Interleaver

Table 3

Comparison between this paper and the existing block interleaving design.

	Standard	Technology (nm)	Memory size	Total size	Operating frequency	Power
[23]	MB-OFDM	FPGA	—	—	500MHz	294.21 mW
[24]	LTE	FPGA	—		100MHz	—
[24]	LTE	FPGA	—		150MHz	—
[10]	802.11n	FPGA	3888 bits		400MHz	10.8 mW
This paper	LTE&5G NR	28	25Kbits		50MHz	6.45 mW