Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP

<div>Distribution of gates in the evolved 5-bit circuits for power functions (<i>x</i><sup>2</sup>, <i>x</i><sup>3</sup>, and <i>x</i><sup>4</sup>), with (a) showing circuits obtained using BwF, and (b) showing circuits using SL for evolutionary strategy (10 ⟶ (1 + 10), 28 ⟶ (2 + 8), 55 ⟶ (5 + 5)).</div>

IET Computers & Digital Techniques

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Figure 4

Figure 4: Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP 