Journals
Publish with us
Publishing partnerships
About us
Blog
IET Computers & Digital Techniques
Journal overview
For authors
For reviewers
For editors
Table of Contents
Special Issues
IET Computers & Digital Techniques
/
2024
/
Article
/
Fig 7
/
Research Article
Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP
Figure 7
Example showing CGP evolved circuit for 4-bit sigmoid function using (a) selected gates from standard cells and (b) basic gates.
(a)
(b)