Design of Ultrasmall Plasmonic Logic Gates Based on Single Nanoring Dielectric-Metal-Dielectric Waveguide

Sadeq, Salma Ali; Hayati, Mohsen; Khosravi, Saba

doi:https://doi.org/10.1155/2023/4489791

International Journal of Optics

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Abstract Introduction Conclusion Data Availability Conflicts of Interest Acknowledgments References Copyright Related Articles

Research Article | Open Access

Volume 2023 | Article ID 4489791 | https://doi.org/10.1155/2023/4489791

Design of Ultrasmall Plasmonic Logic Gates Based on Single Nanoring Dielectric-Metal-Dielectric Waveguide

Salma Ali Sadeq,¹Mohsen Hayati,¹and Saba Khosravi¹

Academic Editor: Nicola Curreli

Received28 Aug 2023

Revised06 Oct 2023

Accepted28 Oct 2023

Published21 Nov 2023

Abstract

This paper proposes a new configuration of dielectric-metal-dielectric (DMD) waveguides to design optical logic gates. Seven plasmonic logic gates, including NOT, OR, AND, NAND, NOR, XOR, and XNOR, are realized by one nanoring and four DMD plasmonic waveguides. To realize the logic gates, an ultrasmall size of 300 nm × 300 nm device is designed. The performance of the plasmonic logic gates is based on constructive and deconstructive interference between input and control ports. To evaluate the logic state of the output port, the threshold transmission limit is assumed to be 0.35. The transmission ratio, T, contrast ratio, CR, modulation depth, MD, insertion loss, IL, and contrast loss, CL, parameters measure the seven logic gates’ performance. A maximum T of 232% is obtained for AND, OR, and XNOR logic gates. Simulation results show that the dimensional parameters are optimized because of very high MD for all seven logic gates. Maximum values of CR and CL are obtained for the NOT gate. For the AND gate, a minimum IL value is achieved. The studied plasmonic logic gates can be employed in building blocks of all-optical signal-processing nanocircuits and nanophotonics devices. The finite element method (FEM) simulates the structure with COMSOL Multiphysics 5.4 software.

1. Introduction

The surface plasmon polaritons (SPPs) are the waves that propagate on metal-dielectric interfaces due to interactions between electromagnetic waves in dielectric and free electrons in metal. The ability to manufacture the low loss devices with dimensions less than 100 nm and confining the light beyond the diffraction limit lead to the design of all-optical SPP structures [1]. Control of the constructive and destructive interferences between light signals in plasmonic waveguides is the basic idea for designing plasmonic devices [2–5]. In recent years, many passive and active SPP devices such as switches [6, 7], logic gates [5, 8–18], sensors [19, 20], nanowires [21–23], splitters [24], filters [25, 26], couplers [27], resonators [28, 29], and multi- and demultiplexers have been designed [30–33]. In design of plasmonic logic gates, DMD [14, 34–36] and metal-dielectric-metal (MDM) plasmonic waveguides are mostly used [37–44]. DMD plasmonic waveguides offer advantages such as longer propagation length, reduced propagation loss, higher quality factor, improved figure of merit, ease of fabrication, and lower coupling loss [5]. In this way, a NOT plasmonic logic gate based on two nanoring DMD resonators with the size of 350 nm × 350 nm has been designed [34]. The transmission threshold limit has been assumed to be 0.5, and a maximum transmission value of 72% has been obtained. Five optical plasmonic logic gates, consisting of OR, NOR, AND, NAND, and NOT, have been realized by two DMD nanoring resonators [35]. The size of the structure is 200 nm × 400 nm. The transmission threshold value of 0.3 has been considered, and a maximum transmission value of 152% at the resonant wavelength of 1550 nm has been reported. The performance of the plasmonic gates is evaluated by T and CR parameters. DMD square-shaped cavities have been utilized for the design of NOT, OR, AND, NOT-OR, NAND, XOR, and XNOR optical logic gates [36]. The structure with the size of 400 nm × 400 nm has been proposed. The T, CR, MD, and IL parameters are used for evaluating the gate’s performance. Transmission threshold has been assumed to be 0.3, and the transmission peak of 202% at the wavelength of 1310 nm has been obtained. Seven plasmonic logic gates, including NOT, OR, AND, NOT-OR, NAND, XOR, and XNOR, have been designed based on DMD waveguides and four ring resonators [14]. The transmission and extinction ratio (ER) parameters have been used for evaluating the gate’s performance. The size of the structure is 400 nm × 380 nm, and the transmission threshold limit has been assumed to be 0.25. The maximum values of T have been obtained as 239% and 187% at the wavelengths of 900 nm and 1330 nm, respectively.

In this article, seven plasmonic logic gates, including NOT, OR, AND, NOR, NAND, XOR, and XNOR, are designed. The ultrasmall structure with an area of 300 nm × 300 nm based on DMD plasmonic waveguides and single ring resonator is proposed. The threshold transmission value is 0.35 in order to evaluate the output logic state. T, CR, MD, IL, and CL parameters measure all seven logic gates’ performance. The maximum value of T is 232% for AND, OR, and XNOR logic gates at the resonant wavelength of 1310 nm. The simulation results are obtained by the FEM using COMSOL Multiphasic software. This research is considered fundamental for achieving an all-optical computer in the future.

2. Structure Layout and the Theoretical Model

A two-dimensional view of the symmetrically designed optical plasmonic gates with an area of 300 nm × 300 nm is indicated in Figure 1. Symmetrical design supports strong absorption and scattering of light leading to enhance electromagnetic fields near the metal surface [45]. The metal region is assumed to be silver with the dispersive relative permittivity characterized by Johnson and Christy’s data [46]. The dielectric region is flint glass with a refractive index of 1.8 [47, 48]. The structural parameters are the height and width of the structure, H, the length of the side stripes, L_s, the length of the middle stripe, L_m, the nanoring outer radius, b, the nanoring inner radius, a, the width of the strips, , and the distance between the stripes and nanoring, d. The dimensional parameters are listed in Table 1. In the studied structure, two ports are considered input ports; the two other ports are assumed to be output and control ports. The input ports are excited by a transverse magnetic (TM) polarized plane wave with electromagnetic filed components of E_x, E_Y, and H_z, as shown in Figure 1. The equation describing the dispersion relation for the TM mode in the waveguide is as follows [5]:where , , and are the dielectric constant of the insulator, the dielectric constant of the metal, and the thickness of the thin metal layer, respectively. The dielectric wave number, , and the metal wave number, , are linked to the propagation constant of as follows:where is the free space wave number and is calculated as follows:

The effective refractive index of the waveguide for SPPs waves is obtained as follows:

The Maxwell equations have been numerically solved using the two-dimensional FEM (2-D FEM) with the utilization of a convolutional perfectly matched layer (CPML) as the absorbing boundary condition within the simulated area.

The parameters of T, CR, MD, IL, and CL evaluate the optical gate’s performance. T is obtained by outgoing optical power, Pout, and the incoming optical power, Pin, as follows [14]:

The output state of the desired logic gates is determined by the threshold limit value. In our proposed structure, the threshold value is assumed to be 0.35. Therefore, the output state will be logic one or ON when the transmission ratio is greater than the threshold limit. If the transmission ratio is smaller than the threshold limit, the output state is interpreted as logic 0 or OFF.

The CR is defined as follows [49]:where Pout | ON_min is the minimum output power of the output port for a logic state of 1 and Pout | OFF_max is the maximum output power of the output port for a logic state of 0.

The relationship between the maximum transmission in the ON state, Max T_ON, and the minimum transmission in the OFF state, Min T_OFF, is described by the MD parameter obtained as follows [40]:

Another parameter is IL defined as the loss in signal power from the input port to the minimum transmission of the output port in the case of the ON state. The IL is calculated as follows [50]:

The description of the IL values in dB is given in Table 2.

The new parameter is CL, which measures the losses due to the CR; when the CR is high and IL is low, the induced losses are low and vice versa. The CL is defined as follows [50]:

Explanation of the values for the CL parameter is given in Table 3.

The structure performance is based on constructive and destructive interferences between the control signal and the input signal(s). The destructive and constructive interferences between the control signal and the input(s) depend on the position of the control and the input ports and the phase of the incident signal when the dimensions of the structure, materials, size, and shape are fixed. When the incident waves at the input ports and the selector port have the same phase and direction of propagation, constructive interference occurs. In the case of the phase or direction of the propagation of the incident wave at the input ports and selector ports are different, the destructive interference happens.

Destructive and constructive interference between incident signals is described by the following equation [14]:where m is the interference order as a positive integer greater than zero. n_eff, θ, and λ are the effective refractive index of the silver material, the phase of the incident wave, and the incident wavelength, respectively.

3. Parameters Validation

This section provides a detailed explanation of the approach utilized to determine the parameter dimensions of the proposed structure, as depicted in Figure 1, which operates at the wavelength of 1310 nm. The geometrical parameters of W, L_s, L_m, a, and d are considered.

For optimal performance in the suggested structure, as illustrated in Figure 2, it is recommended to configure the W parameter at 15 nm. This specific width value guarantees resonance at the desired wavelength and maximizes the transmission efficiency.

Furthermore, within the suggested framework, optimal transmission at the wavelength of 1310 nm is achieved by adjusting the L_s to a value of 160 nm, as illustrated in Figure 3. It is worth mentioning that when the side stripes are extended beyond a length of 160 nm, there is an observed displacement of the resonance wavelength towards the longer wavelength. Conversely, a reduction in the length of the side stripes below 160 nm leads to a displacement of the resonance wavelength towards the shorter wavelength.

As depicted in Figure 4, the transmission values remain consistent across all three options for the length of the middle stripes in the proposed structure. Specifically, the Lm is set at 105 nm, which leads to a 5 nm separation distance (d) between all stripes and the resonator, simplifying the structure.

In contrast, the proposed structure exhibits its highest transmission at the 1310 nm wavelength when the inner radius of the nanoring is set to 30 nm, as depicted in Figure 5. However, if the length of the side stripes is extended beyond 30 nm, it causes a shift towards longer wavelengths in the resonance. Conversely, decreasing the length of the side stripes below 30 nm causes a shift towards shorter wavelengths in the resonance. Upon establishing the optimal values for the parameters (a) and (d), it can be inferred that the most favorable choice for the outer radius of b is 40 nm. Consequently, for this investigation’s proposed structure, the selected dimensions of W, L_s, L_m, a, b, and d are set at 15, 160, 105, 30, 40, and 5 nm, respectively.

4. Design of Optical Gates

The performance of seven plasmonic logic gates, including NOT, OR, AND, NOR, NAND, XOR, and XNOR gates, is determined by choosing input, output, and control ports. The studied wavelength range for the input and control ports is 1000–1800 nm.

4.1. Plasmonic NOT Logic Gate

A schematic of the NOT gate circuit symbol with the truth table is shown in Figure 6. For the NOT gate performance, ports 1 and 2 are considered as the control ports and ports 3 and 4 are input and output ports, respectively. According to the truth table, if the input port is OFF, logic 0, the output port will be ON, logic 1. When the input port state is ON, the output port state is OFF.

(a)

(b)

The transmission spectrum for the NOT gate is indicated in Figure 7. In the case of the control, ports 1 and 2 are excited by an incident light of wavelength 1310 nm with a phase angle of 180° and 45°, respectively, and when the input port state is ON, destructive interference occurs between the input signal and the two control signals. At the wavelength of 1310 nm, the transmission value is 0.056, less than the transmission threshold of 0.35. Therefore, the state of the output port is OFF.

Constructive interference occurs if the state of the input port is OFF and the state of the control ports is ON with a phase shift of 0°. The transmission value is 1.55 and greater than the transmission threshold of 0.35 at the wavelength of 1310 nm. In this case, the output port is ON.

The z component of the magnetic field distribution, Hz, while the input port state is ON and OFF is shown in Figures 8(a) and 8(b), respectively.

(a)

(b)

The simulation results of the NOT logic gate are summarized in Table 4.

According to the results, the CR of the NOT logic gate is high, 15 dB; therefore, the gate’s performance is very good and efficient [49]. The gate is designed with optimum dimensions because of the very high MD of 96.77% [40]. According to Table 2, an ultralow IL value of −1.9 dB is obtained. Also, a CL value of 16.9 dB is achieved, which means that the NOT gate CL parameter is excellent and efficient, as provided in Table 3 [50].

4.2. Plasmonic OR Logic Gate

The conventional circuit symbol of the OR logic gate and the truth table are indicated in Figures 9(a) and 9(b), respectively. The output logic is 1 if both inputs or one of the inputs is ON. When both inputs are OFF, the output state is OFF.

(a)

(b)

In the proposed structure, ports 1 and 2 are input ports as input 1 and input 2, respectively. The port 3 and 4 are the control port and the output port, respectively. The transmission spectrum of the OR plasmonic gate is shown in Figure 10.

When the input ports are OFF and the control port is ON with the phase of 0°, the output is OFF. As shown in Figure 10, for the transmission spectrum, the transmission is 0.07, less than the transmission threshold of 0.35. Therefore, the output port state is logic 0. In the case of one of the input ports being ON and there is no phase difference between the ON input port and control port, constructive interference occurs. Therefore, the transmission reaches 0.81 and the state of the output port is ON. As shown in Figure 10, when both input ports are ON, the transmission peak is 2.32. Because there is no phase difference between input ports and control ports, constructive interference between the input and control ports occurs and the greatest transmission value of 2.32 is obtained.

The z component of the magnetic field distribution, Hz, when the input ports are OFF and ON is shown in Figures 11(a) and 11(b), respectively.

(a)

(b)

The simulation results of the OR logic gate are provided in Table 5.

For the plasmonic OR logic gate, the CR is medium. Therefore, the gate performance is good and efficient [49]. The MD of 96.95% shows an excellent design with optimal dimensions [40]. Low IL is obtained for the optical gate. According to Table 3, good CL is achieved [50].

4.3. Plasmonic AND Logic Gate

The AND logic gate circuit symbol and the truth table are shown in Figures 12(a) and 12(b), respectively. Ports 1 and 2 are used as input ports to design the gate. Ports 3 and 4 are assumed to be control and output ports, respectively.

(a)

(b)

The transmission spectrum of the AND logic gate is shown in Figure 13. Constructive interference happens when there is no phase difference between the input and control signals. According to the transmission spectrum, if the input ports and control port with the same phase shift of 180° is ON, the transmission is 2.32, logic 1 at the wavelength of 1310 nm.

Deconstructive interference occurs because of a phase difference between the input and control signals. Therefore, the output port state is logic 0. For the second and third cases given in the truth table, the ON input port with the phase of 45° and the control port phase of 180° are considered. As shown in Figure 13, the peak of the transmission is 0.11, equivalent to logic 0. In the case of both input ports being OFF and the phase of the control port being 180°, the transmission peak is 0.078, equivalent to logic 0.

In the case of the input ports being OFF and ON, the z component of the magnetic field distribution, Hz, is shown in Figures 14(a) and 14(b), respectively.

(a)

(b)

For the AND plasmonic gate, the simulation results are listed in Table 6.

The CR of this logic gate is high; the gate is interpreted as a very good and efficient gate [49]. Excellent design with optimum dimensions is realized because of very high MD [40]. The ultralow IL results in an excellent and efficient CL value [50].

4.4. Plasmonic NOR Logic Gate

A schematic of the NOR gate circuit symbol with the truth table is shown in Figure 15. In this gate, ports 2 and 3 are assumed to be the input ports. The ports 1 and 4 are the control and output ports, respectively. For this gate, the control port is assumed to be ON with a phase shift of 180°. The transmission spectrum of the gate is shown in Figure 16.

(a)

(b)

As shown in Figure 16, when the input ports are OFF, the transmission peak is greater than the transmission threshold and the output state is ON. The peak of transmission is 0.39. In other cases, deconstructive interference occurs between the control and the input signals. If only one of the input ports is ON with the phase of 0°, the transmission value is less than the threshold transmission value due to the phase difference between the ON input port and the control port. At 1310 nm wavelength, the transmission values for cases 2 and 3 are 0.11 and 0.003, respectively. In the case of the input ports being ON, the port 2 with the phase of 45° and the port 3 with the phase of 0° are considered. The peak of the transmission is 0.05. Deconstructive interference occurs because of the phase difference between the ON input ports and the control port.

The z component of the magnetic field distribution, Hz, when the input ports are OFF and ON, is shown in Figures 17(a) and 17(b), respectively.

(a)

(b)

The simulation results of the NOR logic gate are listed in Table 7.

This logic gate has a medium CR [49]. Therefore, the performance of this gate is moderate. An excellent design with optimum dimensions is done due to very high MD of 99.23 [40]. According to Tables 2 and 3, the IL and CL values are acceptable.

4.5. Plasmonic NAND Logic Gate

The conventional symbol of the NAND logic gate and the truth table are shown in Figures 18(a) and 18(b), respectively. To design the gate, the ports 2 and 3 are input ports. Port 1 and port 4 are assumed to be the control port and the output port, respectively. The control port is assumed to be ON with the phase of 0°.

(a)

(b)

The transmission spectrum of the designed gate is shown in Figure 19. In the case of both input ports being OFF and the control port being ON with the phase of 0°, there is only one effective light source and no interference occurs. Therefore, the output port will be in the ON state and the transmission peak is 0.39 at the wavelength of 1310 nm. When only one of the input ports is ON with the phase of 0°, constructive interference occurs between the signals of the input and control ports. As shown in Figure 19, the peak of the transmission is greater than the threshold limit and the output state becomes ON. If port 1 is ON and port 4 is OFF, the peak of the transmission is 0.81. When port 1 is OFF and port 4 is ON, the transmission peak is 1.54.

When the state of the input ports is ON with a difference phase, port 1 with the phase of 180° and port 4 with the phase of 90°, destructive interference occurs and the state of the output port is OFF. In this case, the transmission peak is 0.07.

Figures 20(a) and 20(b) show the z component of the magnetic field distribution, Hz, when the input ports are OFF and ON, respectively.

(a)

(b)

The simulation results of the NAND logic gate are summarized in Table 8.

According to Table 8, the CR of this logic gate is medium. Therefore, its performance is moderate [49]. The MD is very high, and an excellent design with the best dimensions is carried out [40]. According to Tables 2 and 3, the IL and contrast loss values are acceptable [50].

4.6. Plasmonic XOR Logic Gate

A schematic of the XOR gate circuit symbol with the truth table is shown in Figure 21. For the XOR gate performance, ports 1 and 2 are considered as the input ports and ports 3 and 4 are the control and output ports, respectively. The control port is assumed to be ON with the phase of 0°.

(a)

(b)

The transmission spectrum of this plasmonic logic gate is illustrated in Figure 22. According to Figure 22, if the input ports are OFF, no interference occurs. The transmission peak is 0.07, and the output state is OFF. When only one of the input ports is ON, constructive interference occurs between the input and control signals and the transmission peak is 0.81. Therefore, the output state is ON. If port 1 is ON with a phase of 180° and port 2 is ON with a phase of 45°, destructive interference occurs because of the phase difference between the input and control signals. In this case, the transmission peak is 0.05 and the state of the output port is OFF.

Figures 23(a) and 23(b) show the z component of the magnetic field distribution, Hz, when the input ports are OFF and ON, respectively.

(a)

(b)

The simulation results of the XOR logic gate are listed in Table 9.

For this plasmonic logic gate, the CR is medium. Therefore, the gate performance is good and efficient [49]. The MD is very high, so the gate design and dimensions are optimized [40]. The IL is low, according to Table 2. As given in Table 3, the CL is good [50].

4.7. Plasmonic XNOR Logic Gate

The conventional symbol of the XNOR logic gate and the truth table are shown in Figures 24(a) and 24(b), respectively. In order to design the gate, ports 2 and 3 are used as input ports. Ports 1 and 4 are assumed to be the control port and output port, respectively. The control port is assumed to be ON with a phase of 180°.

(a)

(b)

The transmission spectrum of the designed gate is shown in Figure 25. When the input ports are OFF, the applied light at the control port is sufficient to make the transmission peak, 0.39, greater than the threshold limit and the output port is ON. In the case of only one of the input ports being ON with the phase of 45°, destructive interference occurs between the input port signal and the control port. Therefore, the state of the output port is OFF. The transmission peak is given in Table 10. The constructive interference between the input ports and control port occurs if both input ports are ON with the same phase of 180°. Therefore, the transmission peak is 2.32, and the output port state is ON.

Figures 26(a) and 26(b) show the z component of the magnetic field distribution, Hz, when the input ports are OFF and ON, respectively.

(a)

(b)

The results of the XNOR logic gate are provided in Table 10.

The CR of this logic gate is medium, so the gate performance is moderated [49]. Very high MD indicates an excellent design with optimum dimensions [40]. The IL is high, and the CL is very low. According to Tables 2 and 3, the IL and the CL values are acceptable [50].

5. The Comparison of the Proposed Design and Some Works

The plasmonic waveguide type, the number of resonators, the number of proposed logic gates, the size, the transmission threshold limit, the performance evaluation, the maximum of transmission, and the complexity in our work are compared with those in other works listed in Table 11.

6. Conclusion

In this paper, a new design of seven plasmonic logic gates, NOT, OR, AND, NOR, NAND, XOR, and XNOR, is done. The ultrasmall structure with 300 nm × 300 nm size based on DMD plasmonic waveguides is proposed. The threshold transmission value is assumed to be 0.35 for evaluating the logic state of the output. The T, the CR, the MD, the IL, and the CL parameters evaluated all seven logic gates’ performance. The maximum transmission ratio is obtained for AND, OR, and XNOR logic gates. Very high MD is calculated for all seven gates. For the NOT gate, maximum values of CR and CL are measured. For the AND gate, a minimum IL value is obtained. The designed logic gates can be employed in all-optical signal-processing nanocircuits and nanophotonics structures.

Data Availability

The data used to support the findings of this study are available from the corresponding author upon request.

Conflicts of Interest

The authors declare that they have no conflicts of interest.

Acknowledgments

This work was done in the Department of Electrical Engineering, Faculty of Engineering, Razi University, Kermanshah 6714414971, Iran.

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Copyright © 2023 Salma Ali Sadeq et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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