Research Article
Design of Ultrasmall Plasmonic Logic Gates Based on Single Nanoring Dielectric-Metal-Dielectric Waveguide
Table 4
Summarized simulation results for the NOT gate.
| | Input (port 3) | Control 1 (port 1) | Control 2 (port 2) | Output (port 4) | Transmission threshold | T | CR (dB) | MD (%) | IL (dB) | CL (dB) |
| | OFF | ON (180°) | ON (180°) | ON | 0.35 | 1.55 | 15 | 96.77 | −1.9 | 16.9 | | ON (0°) | ON (180°) | ON (45°) | OFF | 0.05 |
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