Research Article
Design of Ultrasmall Plasmonic Logic Gates Based on Single Nanoring Dielectric-Metal-Dielectric Waveguide
Table 5
Summarized simulation results of Figure
9.
| | Input 1 (port 1) | Input 2 (port 2) | Control (port 3) | Output (port 4) | Transmission threshold | T | CR (dB) | MD (%) | IL (dB) | CL (dB) |
| | OFF | OFF | ON (0°) | OFF | 0.35 | 0.07 | 10.6 | 96.95 | 0.9 | 9.7 | | OFF | ON (0°) | ON (0°) | ON | 0.81 | | ON (0°) | OFF | ON (0°) | ON | 0.81 | | ON (0°) | ON (0°) | ON (0°) | ON | 2.32 |
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