Research Article
Design of Ultrasmall Plasmonic Logic Gates Based on Single Nanoring Dielectric-Metal-Dielectric Waveguide
Table 6
The simulation results of the AND plasmonic gate.
| | Input 1 (port 1) | Input 2 (port 2) | Control (port 3) | Output (port 4) | Transmission threshold | T | CR (dB) | MD (%) | IL (dB) | CL (dB) |
| | OFF | OFF | ON (180°) | OFF | 0.35 | 0.078 | 13.2 | 96.63 | −3.65 | 16.85 | | OFF | ON (45°) | ON (180°) | OFF | 0.11 | | ON (45°) | OFF | ON (180°) | OFF | 0.11 | | ON (180°) | ON (180°) | ON (180°) | ON | 2.32 |
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