Research Article
Design of Ultrasmall Plasmonic Logic Gates Based on Single Nanoring Dielectric-Metal-Dielectric Waveguide
Table 8
Summarized simulation results for the NAND logic gate.
| | Input 1 (port 2) | Input 2 (port 3) | Control (port 1) | Output (port 4) | Transmission threshold | T | CR (dB) | MD (%) | IL (dB) | CL (dB) |
| | OFF | OFF | ON (0°) | ON | 0.35 | 0.39 | 7.5 | 95.45 | 4.09 | 3.41 | | OFF | ON (0°) | ON (0°) | ON | 0.81 | | ON (0°) | OFF | ON (0°) | ON | 1.54 | | ON (180°) | ON (90°) | ON (0°) | OFF | 0.07 |
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