A Methodology for an FPGA Implementation of a Programmable Logic Controller to Control an Atomic Layer Deposition System

Algorithm 1

Pseudocode for steps taken to convert LDs to Verilog HDL.

(1)	function Ladder2Verilog(L5X_filename)
(2)
(3)	Find physical IOs, logical rungs, and function modules information
(4)
(5)
(6)
(7)	Assign physical IOS to FPGA pins
(8)	for all rungs do
(9)	Convert to
(10)	Make list from
(11)	Create Verilog from
(12)	Construct Verilog assignment statements
(13)	end for
(14)	Add assigning memory registers to
(15)	Create register declarations and reset assignments
(16)	Create function module instantiations
(17)	for all placeholders do
(18)
(19)	end for
(20)
(21)	end function