Research Article
Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation
Listing 3
Register Description in Opencores Ethernet Tri Mode.
| (1) | module RegCPUData (…, RegInit, RegOut, …); | | (2) | … | | (3) | input [15 : 0] RegInit; | | (4) | output [15 : 0] RegOut; | | (5) | … | | (6) | always @ (posedge Reset or posedge Clk) | | (7) | if (Reset) | | (8) | RegOut <= RegInit; | | (9) | else if (<conditions>) | | (10) | RegOut <= CD_in_reg; | | (11) | endmodule |
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