Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation

Table 1

Overview of identified open-source Ethernet MAC IP cores.

Project	Analyzed version	Version date	License	Language	Documentation^a	Testbench	Ref. impl.
An Ethernet Controller [24]	b2a334d (git)	2019-05-24	BSD 2-clause	Chisel	CC, R	Yes	—
Ariane-Ethernet [25]	ff9710f (git)	2019-02-06	MIT	System Verilog	—	—	—
Gaisler GRETH [26]	2020.4-b4261	2020-12-15	GPL	VHDL	CC, LF	—	Yes
LeWiz LMAC1 [27]	ac5c2ef (git)	2019-05-17	LGPL	Verilog	CC, LF, R	Yes	Yes
LeWiz LMAC2 [28]	07725d4 (git)	2019-01-25	LGPL	Verilog	CC, LF, R	Yes	Yes
LeWiz LMAC3 [29]	852c99b (git)	2019-07-31	LGPL	Verilog	CC, LF, R	Yes	Yes
Litex Liteeth [30]	435c67d (git)	2021-05-27	BSD 2-clause	Migen	CC, R	Yes	Yes
NFMAC10G [31]	c21bfea (git)	2016-02-25	NetFPGA	Verilog	CC, R	Yes	—
Opencores Ethernet Tri Mode [32]	33 (svn)	2009-03-09	LGPL	Verilog	CC, LF	Yes	—
Opencores Ethmac [33]	368 (svn)	2012-02-14	LGPL	Verilog	CC, LF, R	Yes	—
Opencores Gbiteth [34]	3 (svn)	2013-08-23	LGPL	VHDL	CC	—	—
Opencores Minimac [35]	3 (svn)	2010-08-24	GPL	Verilog	CC, LF	Yes	—
Opencores XGE_LL_MAC [36]	2 (svn)	2012-12-01	LGPL	Verilog	CC	—	—
Opencores XGE_MAC [37]	31 (svn)	2017-03-15	LGPL	Verilog	CC, LF, R	Yes	—
P. Kerling Ethernet MAC [38]	b4cf145 (git)	2015-09-08	BSD-derived	VHDL	CC, LF, R	Yes	—
Verilog-Ethernet [39]	b09e01b (git)	2021-06-03	MIT	Verilog	CC, R	Yes	Yes
WGE 100 [40]	4c5ec19 (git)	2012-01-07	BSD 3-clause	Verilog	CC, LF	Yes	—
WhiteRabbit [41]	69cc4cc3 (git)	2017-12-18	LGPL	VHDL	CC, LF	Yes	Yes

^aCC = code comments, R = readme file, and LF = long-form documentation.