Research Article

Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation

Table 10

CDC warning description.

IDSeverityDescription

CDC-1CriticalA single-bit CDC path is not synchronized or has unknown CDC circuitry
CDC-2WarningA single-bit CDC path is synchronized with a 2+ stage synchronizer but the ASYNC_REG property is missing on all or some of the synchronizer flip-flops
CDC-4CriticalA multi-bit bus CDC path is not synchronized or has unknown CDC circuitry
CDC-5WarningA multi-bit bus CDC path is synchronized with a 2+ stage synchronizer but the ASYNC_REG property is missing on all or some of the synchronizer flip-flops
CDC-6WarningA multi-bit bus CDC path is synchronized with a 2+ stage synchronizer and the ASYNC_REG property is present
CDC-7CriticalAn asynchronous signal (clear or preset) is not synchronized or has unknown CDC circuitry
CDC-10CriticalCombinatorial logic has been detected in the fan-in of a synchronization circuit
CDC-11CriticalA fan-out has been detected before a synchronization circuit
CDC-12CriticalData from multiple clocks are found in the fan-in of a synchronization circuit
CDC-13Critical1-bit CDC detected on a non-FD primitive
CDC-14CriticalMulti-bit CDC detected on a non-FD primitive
CDC-15WarningClock-enable controlled CDC
CDC-26WarningRAM-to-FD CDC: LUTRAM read/write potential collision