Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation

Table 2

Features of identified open-source Ethernet MAC IP cores.

Project	Speed	PHY interface	Control interface	Data interface	Primitives
An Ethernet Controller [24]	10/100	MII	OCP	OCP-master	—
Ariane-Ethernet [25]	10/100, 1 G	RGMII	Other address/data bus	Other address/data bus	Xilinx
Gaisler GRETH [26]	10/100	MII, RMII	APB	AHB-master	—
LeWiz LMAC1 [27]	10/100, 1 G	XGMII	RTL	AXI-Stream, RTL + int. FIFO IF	—
LeWiz LMAC2 [28]	>1 G	XGMII	RTL	AXI-Stream, RTL + int. FIFO IF	—
LeWiz LMAC3 [29]	>1 G	CGMII	RTL	AXI-Stream, RTL + int. FIFO IF	—
Litex Liteeth [30]	10/100, 1 G	MII, {G, RG} MII	Wishbone	Wishbone-slave	Xilinx
NFMAC10G [31]	>1 G	XGMII	RTL	AXI-Stream	—
Opencores Ethernet Tri Mode [32]	10/100, 1 G	MII, GMII	Other address/data bus	Int. FIFO IF	Intel, Xilinx
Opencores Ethmac [33]	10/100	MII	Wishbone	Wishbone-master	—
Opencores Gbiteth [34]	10/100, 1 G	RGMII	Wishbone	Wishbone-master	Intel
Opencores Minimac [35]	10/100	MII	Other address/data bus	Wishbone-master	—
Opencores XGE_LL_MAC [36]	>1 G	XGMII	RTL	Ext. FIFO IF	—
Opencores XGE_MAC [37]	>1 G	XGMII	Wishbone	Int. FIFO IF	—
P. Kerling Ethernet MAC [38]	10/100, 1 G	MII, GMII	RTL	Ext. FIFO IF, int. FIFO IF	Xilinx
Verilog-Ethernet [39]	10/100, 1 G, >1 G	MII, {G, RG, XG}MII	RTL	AXI-Stream	Intel, Xilinx
WGE 100 [40]	10/100, 1 G	MII, GMII	RTL	Ext. FIFO IF	Xilinx
WhiteRabbit [41]	1 G	PCS	Wishbone	Wishbone	—