Research Article
Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation
Table 3
Extended features of identified open-source Ethernet MAC IP cores.
| Project | MDIO | Default datapath width (bits) | DMA | RX FIFO | TX FIFO | RX RAM buffer | TX RAM buffer | FCS | VLAN | PTP support | MAC address filtering | MAC address insertion | Half duplex |
| An Ethernet Controller [24] | — | 32 | Yes | — | — | — | — | — | — | — | — | — | — | Ariane-Ethernet [25] | Yes | 64 | — | Yes | Yes | Yes | Yes | Yes | — | — | Yes | — | — | Gaisler GRETH [26] | Yes | 32 | Yes | Yes | Yes | — | — | Yes | — | — | Yes | — | Yes | LeWiz LMAC1 [27] | — | 64 | — | Yes | Yes | — | — | Yes | Yes | — | Yes | Yes | — | LeWiz LMAC2 [28] | — | 64 | — | Yes | Yes | — | — | Yes | Yes | — | Yes | Yes | — | LeWiz LMAC3 [29] | — | 256 | — | Yes | Yes | — | — | Yes | Yes | — | Yes | Yes | — | Litex Liteeth [30] | Yes | 32 | — | Yes | Yes | Yes | Yes | Yes | — | — | — | — | — | NFMAC10G [31] | — | 64 | — | Yes | Yes | — | — | Yes | — | — | — | — | — | Opencores Ethernet Tri Mode [32] | Yes | 32 | — | Yes | Yes | — | — | Yes | — | — | Yes | Yes | Yes | Opencores Ethmac [33] | Yes | 32 | Yes | Yes | Yes | — | — | Yes | — | — | Yes | Yes | Yes | Opencores Gbiteth [34] | Yes | 32 | Yes | Yes | — | Yes | Yes | Yes | Yes | — | Yes | — | — | Opencores Minimac [35] | Yes | 32 | Yes | Yes | Yes | — | — | — | — | — | — | — | — | Opencores XGE_LL_MAC [36] | — | 64 | — | — | — | — | — | Yes | — | — | — | — | — | Opencores XGE_MAC [37] | — | 64 | — | Yes | Yes | — | — | Yes | — | — | — | — | — | P. Kerling Ethernet MAC [38] | Yes | 8 | — | Yes | Yes | — | — | Yes | — | — | Yes | Yes | — | Verilog-Ethernet [39] | — | 64, 8 | — | Yes | Yes | — | — | Yes | — | Yes | — | — | — | WGE 100 [40] | Yes | 32 | — | Yes | Yes | — | — | Yes | — | — | Yes | — | — | WhiteRabbit [41] | — | 16 | — | Yes | Yes | — | — | Yes | Yes | Yes | — | — | — |
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