Research Article

Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation

Table 4

OOC synthesis resource results.

ProjectVariantLUTsFFsLatchesCARRY4SRLLUTRAMBRAM 18KBRAM 36KClock buffers/MUXes

An Ethernet Controller [24]45070401600000
Ariane-Ethernet [25]9437820342160121
Gaisler GRETH [26]1137866054096000
LeWiz LMAC1 [27]LMAC_CORE1_AXIS24214440679738372010000
LeWiz LMAC1 [27]LMAC_CORE1_AXIS_XPM_FIFO57216269156912404120
LeWiz LMAC1 [27]LMAC_CORE_TOP26169342173431861910000
LeWiz LMAC1 [27]LMAC_CORE_TOP_XPM_FIFO4957529715011965100
LeWiz LMAC2 [28]LMAC_CORE_TOP_XPM_FIFO5954632515471965100
LeWiz LMAC3 [29]LMAC_CORE_TOP_XPM_FIFO473002106823083825909510
Litex Liteeth [30]liteeth8966700510801620
Litex Liteeth [30]liteeth-rgmii8676480510801623
NFMAC10G [31]nfmac10g3010120301800000
NFMAC10G [31]nfmac10g_with_user_intf3583225703600020
Opencores Ethernet Tri Mode [32]ethernet_tri_mode1443139906100063
Opencores Ethernet Tri Mode [32]ethernet_tri_mode_single_clk1443139906100063
Opencores Ethmac [33]2179234307600400
Opencores Gbiteth [34]N/AN/AN/AN/AN/AN/AN/AN/AN/A
Opencores Minimac [35]63663701600200
Opencores XGE_LL_MAC [36]249488704700000
Opencores XGE_MAC [37]22861524053048040
P. Kerling Ethernet MAC [38]pkerling_ethernet_mac4352560600002
P. Kerling Ethernet MAC [38]pkerling_ethernet_mac_with_fifos85361706220112
Verilog-Ethernet [39]verilog-ethernet-eth_mac_10g_fifo2953126303200220
Verilog-Ethernet [39]verilog-ethernet-eth_mac_1g_fifo52052204300220
Verilog-Ethernet [39]verilog-ethernet-eth_mac_1g_gmii_fifo53557604300222
Verilog-Ethernet [39]verilog-ethernet-eth_mac_1g_rgmii_fifo55956504300221
Verilog-Ethernet [39]verilog-ethernet-eth_mac_mii_fifo49853804300222
WGE 100 [40]615838066028202
WhiteRabbit [41]wr-endpoint1833163004510400