Research Article
Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation
Table 6
Vivado synthesis warnings.
| Project | Variant | Constraints | Latches | Linting | Optimization | Simulation mismatch | Structural | Unconnected (internal) port |
| An Ethernet Controller | — | — | — | 6 | 12 | — | — | 100+ | Ariane-Ethernet | — | — | — | 2 | 4 | — | — | 21 | Gaisler GRETH | — | — | — | 100+ | 73 | 1 | 18 | 100+ | LeWiz LMAC1 | LMAC_CORE1_AXIS | 2 | 41 | 1 | 100+ | 100+ | — | 100+ | LeWiz LMAC1 | LMAC_CORE1_AXIS_XPM_FIFO | — | 1 | 1 | 88 | — | — | 100+ | LeWiz LMAC1 | LMAC_CORE_TOP | 5 | 33 | 2 | 94 | 96 | — | 100+ | LeWiz LMAC1 | LMAC_CORE_TOP_XPM_FIFO | — | 1 | — | 80 | — | — | 100+ | LeWiz LMAC2 | LMAC_CORE2_TOP_XPM_FIFO | — | 1 | — | 82 | — | — | 100+ | LeWiz LMAC3 | LMAC_CORE3_TOP_XPM_FIFO | — | 2 | 2 | 100+ | — | — | 100+ | Litex Liteeth | liteeth | — | — | — | 56 | — | — | 16 | Litex Liteeth | liteeth-rgmii | — | — | 6 | 66 | — | — | 12 | NFMAC10G | nfmac10g | — | — | 61 | 2 | — | 2 | 100+ | NFMAC10G | nfmac10g_with_user_intf | — | — | 61 | 2 | — | 2 | 100+ | Opencores Ethernet Tri Mode | clk_reg_is_clk_user | — | — | 35 | 6 | 2 | 12 | 100+ | Opencores Ethernet Tri Mode | clk_reg_is_not_clk_user | — | — | 35 | 6 | 2 | 12 | 100+ | Opencores Ethmac | — | — | — | 1 | 1 | 1 | 1 | 17 | Opencores Gbiteth | — | N/A | N/A | N/A | N/A | N/A | N/A | N/A | Opencores Minimac | — | — | — | 12 | 2 | — | 3 | 80 | Opencores XGE_LL_MAC | xge_ll_mac | — | — | 12 | 3 | 1 | — | 1 | Opencores XGE_MAC | xge_mac | — | — | — | 1 | — | — | 67 | Opencores XGE_MAC | xge_mac_ramstyle | — | — | — | 1 | — | — | 67 | P. Kerling Ethernet MAC | pkerling_ethernet_mac | — | — | 1 | 3 | — | 2 | 6 | P. Kerling Ethernet MAC | pkerling_ethernet_mac_with_fifos | — | — | — | 9 | — | 2 | 6 | Verilog-Ethernet | verilog-ethernet-eth_mac_10g_fifo | — | — | 100+ | 13 | — | 4 | 100+ | Verilog-Ethernet | verilog-ethernet-eth_mac_1g_fifo | — | — | 26 | 10 | — | — | 100+ | Verilog-Ethernet | verilog-ethernet-eth_mac_1g_gmii_fifo | — | — | 26 | 10 | — | — | 100+ | Verilog-Ethernet | verilog-ethernet-eth_mac_1g_rgmii_fifo | — | — | 27 | 11 | — | — | 100+ | Verilog-Ethernet | verilog-ethernet-eth_mac_mii_fifo | — | — | 28 | 10 | — | — | 100+ | WGE 100 | — | — | — | 22 | — | — | 1 | 20 | WhiteRabbit | wr-endpoint | — | 1 | — | 22 | — | 27 | 100+ |
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