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| Category | Warning ID | Warning text |
|
| Constraints | Timing 38–493 | Port name has one or several leaf clock pins in its transitive fan-out without any clock buffer on the path and no clock reaching the clock pin(s). Vivado cannot infer the clock source when no clock buffer is found on the path to a leaf clock pin. |
| Latches | Synth 8–327 | Inferring latch for variable name |
| Linting | Synth 8–151 | Case item value is unreachable |
| Linting | Synth 8–2490 | Overwriting previous definition of module name |
| Linting | Synth 8–2507 | Parameter declaration becomes local in name with formal parameter declaration list |
| Linting | Synth 8–2644 | Root scope declaration is not allowed in Verilog 95/2K mode |
| Linting | Synth 8–3917 | Design name has port name driven by constant value |
| Linting | Synth 8–4747 | Shared variables must be of a protected type |
| Linting | Synth 8–639 | System function call name not supported |
| Linting | Synth 8–689 | Width (N) of port connection name does not match port width (M) of module name |
| Linting | Synth 8–7023 | Instance name of module name has N connections declared, but only M given |
| Optimization | Synth 8–3332 | Sequential element name is unused and will be removed from module name |
| Optimization | Synth 8–3936 | Found unconnected internal register name and it is trimmed from N to M bits |
| Optimization | Synth 8–4446 | All outputs are unconnected for this instance and logic may be removed |
| Optimization | Synth 8–6014 | Unused sequential element name was removed |
| Simulation mismatch | Synth 8–567 | Referenced signal name should be on the sensitivity list |
| Simulation mismatch | Synth 8–5788 | Register name in module name has both set and reset with same priority. This may cause simulation mismatches. Consider rewriting code |
| Simulation mismatch | Synth 8–614 | Signal name is read in the process but is not in the sensitivity list |
| Simulation mismatch | Synth 8–6426 | Mix of sync and async assignments to register name in module name in the same process may cause logic issues |
| Structural | Synth 8–3848 | Net name in module/entity name does not have driver |
| Structural | Synth 8–6104 | Input port name has an internal driver |
| Unconnected (internal) port | Synth 8–3331 | Design name has unconnected port name |
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